This section introduces aspects that may help facilitate a better understanding of the disclosure. Accordingly, these statements are to be read in this light and are not to be understood as admissions about what is or is not prior art.
Lengths of on-chip and off-chip interconnects lead to large capacitance that result in excessive energy consumption. Various approaches have been implemented such as low-swing voltage mode (shown in FIG. 11) and low-swing current mode (shown in FIG. 12). In low-swing voltage mode, a smaller voltage, e.g., 1.2 V (shown as Vlow in FIG. 11), is used and it is stepped up to nominal voltages, e.g., 5 V (shown as VDD in FIG. 11), utilizing a voltage boost circuit known to a person having ordinary skill in the art. In low-swing current mode, the low voltage (shown as Vlow in FIG. 12) is passed through a load resistor (shown as RL in FIG. 12) and the resultant current is converted to a nominal voltage (shown as VDD in FIG. 12) using trans-impedance amplification. However, these approaches still suffer from excessive capacitance and thus energy consumption limiting the length of interconnects, whether on-chip or off-chip. Other approaches may cause too much delay, thereby causing violation of clock edges.
Therefore, there is an unmet need for a novel approach for energizing on-chip and off-chip interconnects that reduces energy consumption when the interconnects are charges and discharged and which does not add clock edge-violating delays.